Electronic design automation (EDA) tools are used to design electronic circuits such as integrated circuits. Integrated circuits can include many thousands and perhaps millions of circuit elements (e.g., transistors, logic gates, diodes, etc.) and interconnecting wires and busses. The circuit elements and wires can be formed on many different layers, with various interconnections (e.g., vias) between layers. EDA tools allow a designer to describe an integrated circuit based on its desired behavior, and then transform that behavioral description into a set of geometric shapes called a layout which forms the circuit elements and wires for all the different layers.
EDA tools further allow certain components to be specified at a high level of abstraction and then replicated many times in the overall integrated circuit, each being called an “instance,” at lower levels of abstraction and placed on different layers of the integrated circuit. Any given instance can include dozens or more geometric shapes, and some shapes in the same instance can be placed in different layers, for example to allow for shapes to be aligned with different tracks or other specified directions associated with different layers. Instances can also include “pins,” which are elements that allow the instance to be connected with other components via wires and busses for example.
As integrated circuit feature sizes continually get smaller and smaller (e.g., 10 nm and below), EDA tools need to be aware of an ever-increasing number of constraints (i.e., design rules or design rule manuals (DRMs)) to ensure that shapes are placed correctly for a target fabrication process. For example, some foundries specify that shapes of a design can only be placed in parallel routing tracks (hereinafter “tracks”) running in one direction of a given layer or portion of a layer and shapes in these tracks must conform to certain legal width requirements (e.g., having a specific one of a number of pre-specified legal widths). Moreover, to allow a design to be implemented by multiple patterning processes (e.g., double patterning, self-aligned double patterning (SADP), etc.), shapes in adjacent tracks of a given layer of an integrated circuit may have alternate colors (e.g., B for shapes to be included in a “blue” photomask, C for shapes to be included in a “cyan” photomask, etc.) and the widths for shapes in adjacent tracks may need to conform to further requirements.
Patterns of tracks can be specified for an integrated circuit design, wherein a set of adjacent tracks have associated widths, spacing and colors (e.g., non-uniform width spacing patterns (WSPs)), and these patterns can be repeated in a given layer with a corresponding period. Tracks themselves have zero width and no components in physical designs (e.g., a layout of an electronic design) and are merely used to guide physical implementation tools (e.g., floorplanner, placement tools, or routing tools) to implement the physical design for an electronic circuit. For example, a routing tool may lay the centerline of a wire segment along a routing track during the routing process. The width associated with a particular routing track is used to route wires having shapes with the associated width.
Track patterns are not always provided by the technology and in those cases they must be created as part of the design process. The process of generating colored track patterns, having non-uniform width and/or spacing, can be very complex.